State of the art electronic design automation (EDA) systems for designing complex integrated circuits (ICs) involves the use of several software tools for the creation and verification of designs of such circuits. Presently, EDA systems implement a design process commonly known as the top-down design methodology. This methodology is an iterative process that includes the processing steps of logic synthesis, floor-planning, place and route, and timing optimization.
The start point of a typical top-down design flow is a register transfer level (RTL) description of a circuit. The RTL description provides a functional view of an IC design expressed in a hardware description language (HDL). The RTL description is then converted, by logic synthesis tools, into detailed gate level netlists. The gate-level netlist is then used to create a floor-plan of the circuit. Thereafter, blocks are placed and routed by place-and-route tools to create the physical layout. The physical layout is optimized through a timing optimization process. To meet design goals the circuit designer defines various design constraints, such as the overall operating frequency of the IC, timing requirements, circuit area, power consumption, and the like. The constraints are used at various stages of the design process.
Generally, design constraints are defined by the circuit designer by means of an ASCII text file, such a Synopsys Design Constraints (SDC) file or Tcl. Typically, a constraints file includes timing assignment information which achieves the following: 1) describing the different attributes of clock signals, such as clock frequency, duty cycle, clock skew, and clock latency; 2) specifying input and output delay requirements of ports relative to a clock transition; and 3) setting timing exceptions. For example, a constraint can be defined using the following self-explanatory format:
set_max_delay 15.0-from [port A]-to [ports B]
The timing constraints can be further generated by design tools used during the various stages of the design. For example, a synthesis tool determines the timing constraints based on statistical wire-load estimation models and pre-characterized cell libraries for the process technology to be used when physically implementing the IC.
In a typical IC design, constraint files are used and modified at various stages of the design. At each stage, the SDC files are cleaned up so as to make them more efficient and concise. In addition, when a designer completes a design stage and moves to the next stage, a new constraint file, that includes constraints that are more appropriate for the new design stage, is generated. Typically, the new file is created either manually by the designer or automatically by using a design tool. For example, a synthesis tool determines the timing constraints based on statistically based wire-load estimation models and cell libraries pre-characterized for the process technology to be used when physically implementing the IC.
To ensure a correct design, it is imperative to check whether a modified or new constraints file meets the design criteria. Currently, an automatic tool that checks for constraints equivalence does not exist in the EDA industry, and such checks are often performed manually by designers, a process which is both time consuming and error prone.
Therefore it would be advantageous to provide a solution for automatically checking for equivalence between two or more constraints files.